Company:
Qualcomm Technologies, Inc.
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary
As a SOC DRAM System Architect, you will define the DRAM controller and PHY architecture for the main memory. In addition, you will work with SoC architects to influence chip architecture to maximize memory performance and power efficiency.
Role and Responsibilities
Define DRAM controller and PHY architecture and microarchitecture to maximize performance and power efficiency
Define microarchitecture of the controller including clocking and low power architecture.
Develop C/C++ models with varying levels of abstraction
Assess PPA trade-offs for various optimization proposals
Collaborate with performance architects to optimize system as well as the simulators
Simulate, analyze and present data to drive decisions
Verify the performance model correlates with the RTL, which may involve writing verification plans, writing directed tests, and writing checkers
Preferred Qualifications
BS/MS/PhD in Computer Science/Computer Engineering/Electrical Engineer with more than 5 years experience in memory controller architecture, microarchitecture or RTL design.
Strong understanding of DDR4 and DDR5 DRAM technologies including 3DS
Strong understanding of various DIMM solutions (RDIMM, LRDIMM)
Expertise in memory controller modeling in C/C++/SystemC
Proficient in scripting languages such as Perl or Python
Experience with productizing DRAM/DIMM solutions for DDR3, DDR4 or similar technologies
Strong understanding of training, calibration and tuning of DRAM interface for stability, performance and power optimization
Expertise with enterprise level RAS solutions for DRAM controllers
Familiarity with high performance and low power design techniques
Experience with the management of various traffic classes
Physical Requirements
Frequently transports and install equipment up to 5 lbs.
Performs required tasks at various heights (e.g. standing or sitting).
Monitors and utilizes computers and test equipment for more than 6 hours a day.
Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.
As a SOC DRAM System Architect, you will define the DRAM controller and PHY architecture for the main memory. In addition, you will work with SoC architects to influence chip architecture to maximize memory performance and power efficiency.
Role and Responsibilities
Define DRAM controller and PHY architecture and microarchitecture to maximize performance and power efficiency
Define microarchitecture of the controller including clocking and low power architecture.
Develop C/C++ models with varying levels of abstraction
Assess PPA trade-offs for various optimization proposals
Collaborate with performance architects to optimize system as well as the simulators
Simulate, analyze and present data to drive decisions
Verify the performance model correlates with the RTL, which may involve writing verification plans, writing directed tests, and writing checkers
Minimum Qualifications
Education:
Bachelors - Computer Science, Bachelors - Electrical Engineering
Work Experiences:
8+ years Systems Engineering or related work experience.
2+ years of experience in one or more system architecture technology areas and products (e.g., Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands).
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