Engineering Group, Engineering Group > CPU Engineering
As a CAD Engineer focusing on timing, you will work with both digital and full custom design leads, tech masters and foundry representatives to help define and implement our methodology and help create the timing flows used by the team. You will be involved from conception to final creation and every step along the way
Roles and Responsibilities
Work with chip leads to understand the design methodology and high level requirements for a timing flow.
Enable multi vendor flow model for STA support
Bring up and support ECO flows working with CAD and design leads
Enable efficient management of disk/ compute/ license and maximize timing runs throughput
MS degree in Electrical Engineering; 10 years of practical experience
Strong fundamentals in digital ASIC design as it relates to timing challenges
Experience with industry standard tools for STA : Primetime, Tempus, etc
Familiar with STA ECO flow and late stage PPA push and design closure
Knowledge of SOC architecture and timing constraining typical paths
Familiarity with high performance and low power design techniques
Some hands-on experience in design verification and/or physical design
Familiar with PPA improvement techniques
Experience with infrastructure necessary for full timing runs at scale
Frequently transports between offices, buildings, and campuses up to ½ mile.
Frequently transports and installs equipment up to 5 lbs.
Performs required tasks at various heights (e.g., standing or sitting).
Monitors and utilizes computers and test equipment for more than 6 hours a day.
Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.
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